1. Field of the Invention
The present invention relates generally to a metallization process for manufacturing semiconductor devices. More particularly, the present invention relates to the metallization of apertures to form void-free interconnects between conducting layers, including contacts and vias in high aspect ratio, sub-half micron applications.
2. Background of the Related Art
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (xe2x80x9cVLSIxe2x80x9d). The multilevel interconnects that lie at the heart of this technology require planarization of high aspect ratio apertures, including contacts, vias, lines or other features having aperture widths less than 0.25 xcexcm and aperture depths greater than the aperture widths. Reliable formation of these interconnects is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Metal interconnects are typically formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), and sequential combinations thereof. Generally, PVD metal films provide superior reflectivity because of better crystalline growth and orientation of the deposited atoms. However, because PVD generally requires atom sputtering from a target in a particular direction, it is difficult to achieve conformal layers on semiconductor features, i.e., a uniform thickness layer on the sides and base of the features. On the other hand, CVD metal films provide excellent conformal coverage of features but poor crystalline orientation and thus low reflectivity.
Aluminum (Al) layers formed by chemical vapor deposition (xe2x80x9cCVDxe2x80x9d), like other CVD processes, provide good conformal aluminum layers for very small geometries, including sub-half micron ( less than 0.5 xcexcm) apertures, at low temperatures. Therefore, CVD of aluminum is a common method used to fill apertures. However, recent transmission electron microscopy data (xe2x80x9cTEMxe2x80x9d) has revealed that voids exist in many of the apertures deposited with CVD Al even though electric tests of these same apertures do not evidence the existence of this void.
FIG. 1 is a partial cross sectional view of a substrate 10 having a via structure 14 formed thereon. A dielectric layer 12 on the surface of the substrate 10, typically etched in a desired pattern, is shown including a via 14 having a high aspect ratio, i.e., a high ratio of via depth to via diameter, typically at least about three (3). A CVD Al film 16 is shown deposited on the substrate and into the via, and a void 18 is formed in the via. It should be recognized that this kind of void is very difficult to detect by regular cross sectional standard electron microscopy (xe2x80x9cSEMxe2x80x9d) techniques, because some deformation occurs in soft aluminum during mechanical polishing. In addition, electric conductivity tests do not detect any structural abnormalities. However, despite the generally positive electric conductivity tests, conduction through the feature having the void may, over time, compromise the integrity of the device.
FIG. 3 is a partial cross sectional view of a substrate 10 having a via structure 20 formed thereon. A dielectric layer on the surface of the substrate 10, typically etched in a desired pattern, is shown including a via 20 having a sub-half micron diameter. A CVD Al film 16 is shown deposited on the substrate and into the via without bridging the via.
A TEM study of various CVD Al layers formed on substrates indicates that the formation of voids occurs through a key hole process wherein the top portion of the via becomes sealed before the via has been entirely filled. Although a thin conformal layer of CVD Al can typically be deposited in high aspect ratio contacts and vias at low temperatures to line the walls and the bottom of the features as shown in FIG. 3, continued CVD deposition to completely fill the contacts or vias typically results in the formation of voids therein as shown in FIG. 1. Extensive efforts have been focused on elimination of voids in metal layers by modifying CVD processing conditions. However, the results have not yielded a satisfactory method of manufacturing void free structures.
An alternative technique for metallization of high aspect ratio apertures is hot planarization of aluminum through physical vapor deposition (xe2x80x9cPVDxe2x80x9d). The first step in this process requires deposition of a thin layer of a refractory metal such as titanium (Ti) on a patterned wafer to form a wetting layer which facilitates flow of the Al during the PVD process. Following deposition of the wetting layer, the next step requires deposition of either (1) a hot PVD Al layer, or (2) a cold PVD Al layer followed by a hot PVD Al layer onto the wetting layer. However, hot PVD Al processes are very sensitive to the quality of the wetting layer, substrate condition, and other processing parameters. Small variations in processing conditions and/or poor coverage of the wetting layer can result in incomplete filling of the contacts or vias, thus creating voids. In order to reliably fill the vias and contacts, hot PVD Al processes must be performed at temperatures above about 450xc2x0 C. Because the PVD wetting process provides poor coverage of high aspect ratio, sub-micron via sidewalls, hot PVD Al does not provide reliable filling of the contacts or vias. Even at higher temperatures, PVD processes may result in a bridging effect whereby the opening of the contact or via is closed because the deposition layer formed on the top surface of the substrate and the upper walls of the contact or via join before the floor of the contact or via has been completely filled.
One attempt at filling high aspect ratio sub-half micron contacts and vias, disclosed in U.S. application Ser. No. 08/561,605, uses a thin bonding layer deposited first over the surface of the contacts or vias, followed by a CVD layer, and then a PVD layer. The thin bonding layer is preferably a metal having a relatively higher melting point temperature than the subsequent CVD and PVD metals. However, the problem of the via or contact opening being bridged by the CVD and PVD processes still remains, and voids may still form in the contacts or vias.
Therefore, there remains a need for a low temperature metallization process for filling apertures, particularly high aspect ratio, sub-half micron contacts and vias. More particularly, it would be desirable to have a low temperature process for filling such contacts and vias with a low temperature CVD Al process and allowing the feature to be planarized with PVD Al to achieve high reflectivity. Furthermore, there is a need to expand the applications for low temperature CVD Al wherein voids formed by the CVD process can be removed regardless of the size of the features. It would be further desirable to have such process incorporating high power PVD to further reduce process time and improve throughput.
The present invention generally provides a low temperature metallization process for filling apertures, particularly high aspect ratio, sub-half micron contacts and vias. More particularly, the present invention provides a low temperature process for filling such contacts and vias with a low temperature CVD Al process and allowing the feature to be planarized with PVD Al to achieve high reflectivity.
One aspect of the invention provides a method for filling an aperture on a substrate by chemical vapor depositing a metal film on a substrate to a sufficient thickness so that there is a continuous film in the aperture which may cause bridging of the aperture and then, annealing the substrate in a low pressure chamber at a temperature below the melting point of the deposited metal film. The invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed CVD film.
Another aspect of the invention expands the applications for low temperature CVD Al wherein voids formed by the CVD process can be removed regardless of the size of the features. The present invention further incorporates high power PVD to deposit a high quality film while further reducing process time and improving throughput.
Yet another aspect of the present invention provides an apparatus for filling an aperture and forming a film over a substrate including a chemical vapor deposition (CVD) chamber for depositing a first film on the substrate, a high vacuum annealing chamber for annealing the substrate and eliminating any voids formed in the first film deposited in the aperture, a physical vapor deposition (PVD) chamber for depositing a planarized film over the first film, and a transfer chamber connected to the CVD chamber, the annealing chamber, and the PVD chamber. The annealing chamber may be a CVD, a PVD chamber or a separate annealing chamber.